Wow. Where do I start? So much software and quite a bit of hardware is used to make the CFT. For now, most of this is merely an outline. It might even stay an outline. I'm sure you can follow links.

A2.1. Software

So. Much. Software. Here's a brief outline of the ones I remember.

A2.1.1. Electronics

Schematics, layout, bills of materials: all done with Eagle, which I've been using for around 18 years

A2.1.2. Graphics Software

• ImageMagick
• XeLaTeX
• PGF/Tikz
• Inkscape
• Gimp

A2.1.3. Typesetting

At one point, I was painstakingly typesetting the CFT book as an actual print book. This web version is considerably uglier, but it's searchable and more people than just me can see it. I used a complicated framework of makefiles running XeLaTeX.

A2.1.4. Video

• KDE's kdenlive. I'm not a fan of video, so I don't really use anything super-fancy. I wouldn't even know if kdenlive is something fancy.

A2.1.5. Programming and scripting languages

• C
• Python
• Bash scripting

A2.2. Hardware

• FlashProg, my shitty Flash programmer.

A2.3. Electronic Components

The CFT mostly uses simple, hand-solderable components and CMOS discrete logic, usually from the ‘HC’ family. Here are some of these referenced throughout this guide. If you don't know these already, you probably shouldn't even be reading this!

A2.3.1. 74HC32 — Hex Or Gates

As basic as they come! This chip contains six independent ‘or’ gates, each with two inputs.

Here's a datasheet.

A2.3.2. 74HC74 — Dual Positive Edge Triggered Flip-Flops

This chip contains two completely independent D type flip-flops, so it holds two bits of state. Each flip-flop has its own data input, inverting and non-inverting outputs, as well as a clock input. Each flip-flop stores the value in D when the clock goes from low to high. The flip-flop can be reset to zero by asserting the clear input. It can be reset to one by asserting the ‘preset’ input. (shouldn't that be ‘set’?) Clear and preset work asynchronously (i.e. independently of the clock input) and override all other behaviour.

I often use these flip-flops to build simple state machines.

Here's a datasheet.

A2.3.3. 74HC85 — 4-bit Magniture Comparator

This chip has two sets of 4-bit inputs A and B. It compares them as 4-bit unsigned integers and outputs three separate, active high signals for the condititons A < B, A = B, and A > B.

These outputs can be connected to the cascade inputs of another 74HC85, which will compare higher order bits. In this way, larger quantities can be compared (provided you can wait for the propagation delay should the first nybbles of the numbers be equal).

I don't really use these much, but there's at least one of them in the Debugging Front Panel (DFP), and it's used to decide whether the processor is in the Fetch or Execute state. The result is displayed on the front panel.

Here's a datasheet — please note, this is for the LS part, not the HC one.

A2.3.4. 74HC112 — Dual Negative Edge Triggered J-K Flip-Flops

This chip contains two completely independent J-K type flip-flops, so it holds two bits of state. Each flip-flop has its own pair of J and K inputs, inverting and non-inverting outputs, as well as a clock input and asynchronous set and clear inputs. When the clock goes from high to low, if J is asserted, the flip-flop is set. If K is asserted, the flip-flop is cleared. If both are asserted, the flip-flop toggles. Clear and preset work asynchronously (i.e. independently of the clock input) and override all other behaviour.

Here's a datasheet.

A2.3.5. 74HC138 — Three-to-Eight Decoder

I'm addicted to those and I think everyone who made digital electronics or interfaced stuff to computers in the Seventies and Eighties is, too. I even have relatively recent PC expansion cards with them on as discrete components!

These chips take three inputs and decode them into eight active-low outputs. When the chip is enabled, exactly one output will ever be asserted. The chip has three enable inputs (two active low, one active high), and all them need to be asserted. When the chip is disabled, all eight outputs are high (deasserted).

These are used for address decoding since they can decode roughly six bits. They can also be abused to simplify some unusual tasks, and I love using them for such things. This is probably why you'll find so many of them in the CFT.

Here's a datasheet.

A2.3.6. 74HC139 — Dual 2-to-4 Decoders

I like to think of the 139 as the 138's idiot brother, but I'm biased. It contains two independent decoders or demultiplexers. Each has two inputs and four outputs. The two input are decoded into the four outputs in the same way as with the 74HC138: the selected output will be low. Unlike the 138, the 193 has a single active-low enable per decoder. This means it can only decode three bits of addressing, but it has many uses nonetheless. (I'm just being needlessly harsh, really)

Here's a datasheet.

A2.3.7. 74HC157 — 8-to-2 Multiplexer

The 157 contains four multiplexers that select between two signals each. A single select input routes either of the two signals to the chip's output. In effect, this chip multiplexes two 4-bit signals into one output.

Here's a datasheet.

A2.3.8. 74HC161 — 4-bit Synchronous Counter

This is a fairly standard 4-bit counter. It counts up in binary, and it can be loaded with arbitrary values. It has two active-high enables (used when cascading multiple counters) and increments its value on the positive edge of its clock.

Here's a datasheet.

A2.3.9. 74HC165 — 8-bit Parallel In Shift Register

This is a shift register that samples 8 bits of input and converts them to a serial signal. The register can be instructed to sample its inputs synchronously. After this, the positive edge of a clock signal shifts the registered bits out. Both normal and complement outputs are available. The clock can be inhibited, and a cascade input is provided so chains of shift registers can be formed.

Besides a useful input shift register, this chip can also help arbitrary 1-to-8 counters, ring counters, and other simple state machines.

Here's a datasheet.

A2.3.10. 74HC175 — 4-bit D Flip-Flop

This chip holds four D type flip-flops, clocked on the positive edge of its CLKsignal. Each flip-flop has its own complementary outputs Q and Q. There is a single asynchronous reset signal, CLR.

Here's a datasheet.

A2.3.11. 74HC193 — 4-bit Up or Down Counter

Using this counter can be a little confusing, but it's very capable. It can count up and down, it can be loaded with any four-bit value you want, it can be cleared asynchronously, and multiple 193s can be connected together to form wider counters using the BORROW and CARRYsignals.

On the CFT it's used both in 4-bit and 16-bit configurations. They're so handy, the processor's registers are built out of them!

Here's a datasheet.

A2.3.12. 74HC251 — 8-to-1 Tri-State Multiplexers

This is a single multiplexer with eight input lines and two output lines. Three selector inputs control which input will be sent to the output. The other output is the complement of the main one. An active-low input allows both outputs to be tri-stated.

The 251 is a very versatile chip, and I only with there were need for more of them in the CFT! Although the CFT uses it as a multiplexer, it can be used as an 8×1 ROM, or a three-input arbitrary gate calculating any function you like—and also returning its complement! Every three-input function can be implemented with a 251.

Here's a datasheet.

A2.3.13. 74HC245 — 8-bit Bidirectional Bus Driver

The 245 is an 8-bit bidirectional bus driver. It contains eight pairs of buffers connecting its A side to its B side and vice versa. An active-low enable signal (OE) and DIR signal controls which pair, if any, will be active:

The net result is that two buses can be connected in the desired direction, or entirely isolated. On the CFT this is used (among other places) as the gateway between the processor's internal bus and the external data bus. Until the end of the Nineties, two of these chips were at the core of every IDE ‘controller’ card for PCs, since the IDE bus was basically nearly identical to the host computer's bus.

Here's a datasheet.

A2.3.14. 74HC253 — Dual 4-to-1 Tri-State Multiplexer

The 253 contains two multiplexers, each of which has four inputs and one output. Two additional inputs select which input will be connected to the output. These selectors are shared between both multiplexers. An additional active-low enable input tri-states the output when it's deasserted. Each multiplexer has separate enables.

This is a handy multiplexer chip, but its best use by far is in implementing arbitrary two-input, two-output Boolean functions. You tie its four inputs to either ground or Vcc, and use the selectors as the two gate inputs.

Here's a datasheet.

A2.3.15. 74HC259 — 8-bit Addressable Latch

This is an 8-bit latch with a twist. Each of its eight bits can be set independently by selecting its address in S0–S2 and setting D appropriately. This only happens when G is low. The addressed nature of the latch makes it ideal as a device controlled, mapped to part of the address bus of a computer.

Here's a datasheet.

A2.3.16. 74HC541 — Octal Tri-State Buffer

This chip packs eight buffers and two active-low enable inputs. When enabled, the outputs follow the inputs (with a modest propagation delay, of course). When either of the two enables is high, all outputs are tri-stated and float freely. Simple stuff.

Here's a datasheet.

A2.3.17. 74HC573 — Octal Latch with Tri-State Outputs

The 573 is an 8-bit latch. When the chip is enabled and its active-high latch control is asserted, the eight outputs follow the inputs. When the latch control is deasserted, the last 8-bit value is retained and the outputs stay constant. The active-low enable signal tri-states the outputs.

I sometimes used this for registering 8-bit values in the CFT. It can be functionally equivalent to an 8-bit flip-flop.

Here's a datasheet.

A2.3.18. 74HC574 — Octal Positive Edge Triggered Flip-Flops

This chip contains eight D type flip-flops with a clock input and an output enable. The chip acts as an 8-bit register, reading its inputs when the clock input goes from low to high. When the enable input is low, the last registered value will be placed on the outputs. When the enable input is high, the outputs are tri-stated.

Here's a datasheet.

A2.3.19. 74HC595 — 8-bit Parallel Out Shift Register

This chip contains a serial in, parallel out 8-bit register. Data is loaded one bit at a time. After all of it is loaded, a signal can be strobed to load the data onto the outputs synchronously. The outputs can be tri-stated, and a cascade output is provided so that multiple chips can be linked to form chains handling multiples of 8 bits. There is also an active low reset signal.

Here's a datasheet.

A2.3.20. 74HC670 — Quad 4-bit

When I got my first databook, this chip jumped right at me and I've wanted to use it in a design ever since. They're hard to find now. This is a 4-bit slice of a register file. It contains four 4-bit registers.

There is a WE signal that enables latching from the four D_1–4 lines to the register selected using the WA_0–1 address lines.

For reading, there is a RE signal that enables or tri-states the outputs (Q_1–4). When RE is low, the register selected using RA_0–1 is output.

Both reading and writing can happen simultaneously. Right about the only thing this chip lacks is a reset input.

Here's a datasheet.

A2.3.21. 74HC688 — 8-bit Comparator

The 688 compares two 8-bit values and outputs an active-low signal when the two values are equal. It has an active-low enable signal. When the signal is high (deasserted), the comparison output will always be high, even when the two 8-bit values are equal.

I don't often have to compare vectors as large as 8 bits, but it sometimes comes in handy. It can be abused to produce an 8-bit AND gate, and also as a zero comparator (there isn't a single gate that does this).

Here's a datasheet.